Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor

ABSTRACT

A semiconductor device  100  comprising a substrate  102  having a through-substrate via hole  106 , the through-substrate via hole  106  having formed therein: a first capacitor electrode layer  110   a  and a second capacitor electrode layer  110   b , and a dielectric material layer  112  disposed between the first capacitor electrode layer  110   a  and the second capacitor electrode layer  110   b ; and a through-substrate via conductor  116 . A method of forming a semiconductor device  100 , the semiconductor device  100  comprising a through-substrate via hole  106 , the method comprising forming, in the through-substrate via hole  106 : a first capacitor electrode layer  110   a  and a second capacitor electrode layer  110   b , and a dielectric material layer  112  disposed between the first capacitor electrode layer  110   a  and the second capacitor electrode layer  110   b ; and a through-substrate via conductor  116.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage filing under 35 U.S.C. 371 ofPCT/SG2016/050461, filed Sep. 21, 2016, which claims priority fromSingapore Patent Application No. 10201507924S, filed Sep. 23, 2015,which applications are hereby incorporated by reference in theirentirety herein.

FIELD OF THE DISCLOSURE

The invention relates generally to semiconductor devices and methods offorming the same. More particularly, the invention relates to formingcapacitor electrode and dielectric layers in a trench formed in asemi-conductor substrate and forming a through-substrate via conductor.

BACKGROUND

Through-substrate-via (TSV) technology is becoming a key enabler for 3-Dchip stacking as well as 2.5D side-by-side integration techniques. Itprovides electrical interconnect between different chip (such as siliconchips) layers vertically. On-chip deep trench capacitors (DTCap) arewidely used in advanced electronic systems for, for example, dynamicrandom access memory (DRAM) and voltage regulator applications, sincethey provide a high capacitance density. Fabricatingthrough-substrate-via and deep trench capacitors can be both challengingand costly, since they can occupy much more die area compared to amodern metal-oxide-semiconductor field-effect transistor (MOSFET).

U.S. Pat. No. 8,492,241 B2 describes a method for simultaneously forminga through-substrate-via and a deep trench structure. Athrough-substrate-via and a deep trench capacitor or a deep trenchisolation (DTI) are simultaneously formed on the same substrate by asingle mask and a single reactive ion etching (RIE). Thethrough-substrate-via trench is wider and deeper that the deep trenchcapacitor or deep trench isolation trench. The through-substrate-via anddeep trench capacitor or deep trench isolation are formed with differentdielectric materials on the trench sidewalls. The through-substrate-viaand deep trench capacitor or deep trench isolation are perfectlyaligned. Supposedly, the cost of fabricating both through-substrate-viaand deep trench capacitor is reduced.

U.S. Pat. No. 8,785,289 B2 illustrates an integrated decouplingcapacitor employing conductive through-substrate-vias. A capacitor in asemiconductor substrate employs a conductive through-substrate-via as aninner electrode and a columnar doped semiconductor region as an outerelectrode. The capacitor provides a large decoupling capacitance in asmall area, and does not impact circuit density or a Si 3D structuraldesign. Additional conductive through-substrate-vias can be provided inthe semiconductor substrate to provide electrical connection for powersupplies and signal transmission there through. The capacitor has alower inductance than a conventional array of capacitors havingcomparable capacitance, thereby enabling reduction of high frequencynoise in the power supply system of stacked semiconductor chips. Thehigh quality deep trench capacitor has electrical connections to bothtop and bottom layers.

U.S. Pat. No. 8,642,456 B2 implements semiconductor signal-capablecapacitors with deep trench and through-substrate-via technologies. Adeep trench N-well structure is formed and an implant is provided in thedeep trench N-well structure with a through-substrate-via formed in asemiconductor chip. At least one angled implant is created around thethrough-substrate-via in a semiconductor chip. The through-substrate-viais surrounded with a dielectric layer and filled with a conductingmaterial which forms one electrode of the capacitor. A connection ismade to one implant forming a second electrode to the capacitor. Thesignal-capable capacitor based on through-substrate-via structure hasmore degree of freedom in terms of electrode connections.

United States Patent Publication No. 20130181326 A1 discloses animproved semiconductor capacitor and method of fabrication. A metalinsulator metal (MIM) stack, comprising alternating first-type andsecond-type metal layers (each separated by dielectric) is formed in adeep cavity. The entire stack can be planarized, and then patterned toexpose a first area, and selectively etched to recess all first metallayers within the first area. A second selective etch is performed torecess all second metal layers within a second area. The etched recessescan be backfilled with dielectric. Separate electrodes can be formed; afirst electrode formed in said first area and contacting all of saidsecond-type metal layers and none of said first-type metal layers, and asecond electrode formed in said second area and contacting all of saidfirst-type metal layers and none of said second-type metal layers.

SUMMARY OF THE INVENTION

The invention is defined in the independent claims. Some optionalfeatures of the invention are defined in the dependent claims.

As disclosed herein, techniques are proposed and described which mayallow co-fabrication of both a capacitor and a TSV in a seam-lessmanner.

Advantages over the known techniques cited above may include one or moreof the following:

-   -   Given that the capacitor electrodes and the TSV conductor occupy        the same trench/through-substrate via hole, these may occupy        significantly less die area; their footprint(s) may be        significantly smaller.    -   The techniques disclosed herein are not limited in respect of no        separated input-output (I/O) signal transfer being possible, as        is the case with some of the prior art techniques.    -   The techniques disclosed herein may be less complex and        difficult to control. Moreover, the disclosed techniques, not        having a particularly wide structure, may be beneficial in that        the compactness and density of the through-substrate-via array        is not so limited.

Implementation of the techniques disclosed herein may providesignificant technical benefits. For instance, a trench structure, suchas a deep trench structure, may be formed within a semiconductorsubstrate. A capacitor may be built within the through-substrate-viahole in which a through-substrate via conductor is also disposed. In atleast one implementation, the capacitor is a multi-layermetal-insulator-metal (MIM) capacitor. This proposed structure maycombine the trench capacitor and the through-substrate-via together inone trench/via hole, but may keep the two terminal electrodes of thethrough-substrate-via conductor and the deep trench capacitor separated.Thus, both the deep trench capacitor and the through-substrate-via canfunction independently.

Further advantages from implementation of the techniques disclosedherein include the following.

There may be cost reduction. By simplifying process flows for theforming of DTCaps and TSVs, fewer masks and processing steps may berequired. Die area is used optimally when combining techniques which,hitherto, have required two trenches.

There may be better thermo-mechanical reliability. In situations wheremore buffering layers are provided in between the substrate and TSVconductor e.g. the conductor core, the thermo-mechanical stress can bemitigated. Thermo-mechanical stress may be introduced in the process ofTSV. In this case, TSV with partially filled copper can mitigate stresslevel as well.

BRIEF DESCRIPTION OF THE FIGURES

The invention will now be described, by way of example only, and withreference to the accompanying drawings in which:

FIG. 1 is a series of diagrams illustrating an exemplary process for theforming of a first semiconductor device;

FIG. 2 is a series of diagrams illustrating a conventional TSV and anexemplary TSV with embedded capacitor;

FIG. 3 is a diagram illustrating an exemplary semiconductor chip stack;

FIG. 4 is a series of diagrams relating to simulation and measurementresults of capacitance density and comparison with known techniques;

FIG. 5 is a series of diagrams illustrating an exemplary process for theforming of a second semiconductor device;

FIG. 6 is a graph illustrating the suppressed capacitance variation withenhanced inner capacitor;

FIG. 7 is a graph illustrating the magnitude and phase of embeddedcapacitors;

FIG. 8 is a diagram illustrating the SPICE model of power distributionnetwork (PDN);

FIG. 9 is a graph illustrating the Impedance reduction due to embeddedcapacitors;

FIG. 10 is a series of graphs illustrating normal stress componentsalong X, Y, Z directions compared with decreasing copper layerthickness;

FIG. 11 is a series of graphs illustrating suppressed mobility variationof transistors towards TSV.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to FIG. 1 as mentioned above, this provides a series ofdiagrams illustrating an exemplary process flow for the forming of afirst semiconductor device 100. FIG. 1(a) shows a substrate 102 having afirst side 102 a and a second side 102 b. In at least oneimplementation, substrate 102 is formed, at least partially, fromsilicon. A window 104 is patterned by photoresist on substrate 102 by,for example lithography. In at least one implementation, the window 104is of a square or generally square shape. In another implementation, thewindow 104 is of a circular or generally circular shape. In FIG. 1(b), atrench 106 is formed in the substrate 102. In one example, the trench106 has a cross-sectional shape corresponding to the shape of thewindow. Trench 106 has an inside surface 106 a. In this example, theinside surface 106 a can be the (or each) sidewall and/or the uppersurface of the bottom of the trench 106. The trench 106 may be formed bya number of known manufacturing techniques including deep reactive ionetching. Concerning dimensions, the trench 106 may be, for example,between 1 μm and 50 μm in diameter, preferably between, say, 5 μm and 20μm, 30 μm or 40 μm. In one preferred arrangement, the trench 106 is 10μm. Preferably, the depth of the trench is between 20 μm and 200 μm,more preferably between 25 μm and 150 μm, yet more preferably between 30μm and 100 μm, and yet more preferably between 40 μm and 75 μm. In oneparticularly preferred arrangement, the trench is 50 μm deep.

A first insulation layer 108 a is formed on at least part of insidesurface 106 a. In the exemplary arrangement of FIG. 1(c), firstinsulation layer 108 a is deposited conformally on the or each sidewalland on the upper surface of the bottom of the trench 106. In thisexample, first insulation layer 108 a is formed as a thin layer, notfilling the trench 106 completely. Optionally, and as illustrated inthis example, insulation layer material is also formed on the uppersurface 106 b of the first side 102 a of substrate 102. A number ofdifferent techniques may be used for the forming of the first insulationlayer 108 a, but one particularly suitable technique is chemical vapourdeposition (CVD). A number of materials may be used to form firstinsulation layer 108 a, such as fluorine-doped silicon oxide (SiOF),Carbon Doped Oxide (CDO), Organo Silicate Glass (OSG) and SiliconOxycarbide (SiOC) but in one preferred arrangement, silicon dioxide(SiO₂) is used as the insulating material. The thickness of firstinsulation layer 108 a is preferably between 0.05 μm and 2 μm, and morepreferably between 0.1 μm and 1 μm. In one exemplary arrangement, thethickness of the layer is 0.2 μm.

As illustrated in FIG. 1(d), a first conductive layer 110 a is formed inthe trench. In this example, first conductive layer 110 a is formed ontop of at least part of first insulation layer 108 a. In at least oneimplementation, the first conductive layer 110 a is formed conformallyon top of the first insulation layer 108 a. In this example, firstconductive layer 110 a is formed as a thin layer, not filling the trench106 completely. Optionally, and as illustrated in this example, firstconductive layer 110 a material is also formed on top of the firstinsulation layer material 108 a formed on the upper surface 106 b of thefirst side 102 a of substrate 102. A number of different techniques maybe used for the forming of the first conductive layer 110 a, but oneparticularly suitable technique is atomic layer deposition (ALD).Additionally or alternatively, first conductive layer 110 a may beformed by sputtering on the structure as shown in FIG. 1(c). As willbecome apparent, first conductive layer 110 a will function as a firstcapacitor electrode layer. A number of materials may be used to formfirst conductive layer 110 a, such as Tantalum Nitride (TaN), Tungsten(W) or Copper (Cu) but in one preferred arrangement, titanium nitride(TiN) is used as the material for the first conductive layer 110 a. Thethickness of the layer is preferably between 0.05 μm and 5 μm, and morepreferably between 0.075 μm and 2.5 μm. In one exemplary arrangement,the thickness of the layer is 0.1 μm.

Thus, it will be appreciated that FIG. 1(d) illustrates semiconductordevice 100 comprising a first insulation layer 108 a disposed on aninside surface 106 a of the trench 106, the first capacitor electrodelayer 110 a being disposed on the insulation layer 108 a.

As illustrated in FIG. 1(e), a dielectric material layer 112 is formedin the trench 106. In this example, dielectric material layer 112 isformed on top of at least part of first conductive layer 110 a. In atleast one implementation, dielectric material layer 112 is formedconformally on top of first conductive layer 110 a. In this example,dielectric material layer 112 is formed as a thin layer, not filling thetrench 106 completely. Optionally, and as illustrated in this example,dielectric material layer 112 is also formed on top of the firstconductive layer 110 a part formed in the area outside of the trench106, above upper surface 106 b on first side 102 a of substrate 102. Anumber of different techniques may be used for the forming of thedielectric material layer 112, but one particularly suitable techniqueis ALD. As will become apparent, dielectric material layer 112 willfunction as a capacitor dielectric. A number of materials may be used toform dielectric material layer 112, but in one exemplary arrangement ahigh-K dielectric material such as aluminium oxide 112 (Al₂O₃) may beused. Alternatively, other materials such as Hafnium (IV) Oxide (HfO₂)or Tantalum Pentoxide/tantalum Oxide Ta₂O₅) may be used. The thicknessof the layer is preferably between 10 nm and 100 nm, more preferablybetween 20 nm and 75 nm, and yet more preferably between 25 nm and 50nm. In one exemplary arrangement, the thickness of the dielectricmaterial layer is 30 nm.

In FIG. 1(f), a second conductive layer 110 b is formed in the trench106. In this example, second conductive layer 110 b is formed on top ofat least part of dielectric material layer 112. In at least oneimplementation, second conductive layer 110 b is formed conformally ontop of dielectric material layer 112. In this example, second conductivelayer 110 b is formed as a thin layer, not filling the trench 106completely. Optionally, and as illustrated in this example, secondconductive layer 110 b is also formed on top of the dielectric materiallayer 112 part formed in the area outside of the trench, above the uppersurface 106 b of first side 102 a of substrate 102. As will becomeapparent, second conductive layer 110 b will function as a secondcapacitor electrode layer, in conjunction with dielectric material layer112 and first conductive layer 110 a. A number of different techniquesmay also be used for the forming of the second conductive layer 110 bbut it may be expedient to use the techniques described above in respectof first conductive layer 110 a. The thickness of the layer ispreferably between 0.05 μm and 5 μm, more preferably between 0.075 μmand 2.5 μm. In one exemplary arrangement, the second conductive layer110 b is 0.1 μm thick. In one exemplary arrangement, TiN may be used asthe first conductive layer. Alternatively, other materials such asTantalum Nitride (TaN), Tungsten (W) or Copper (Cu) may be used.

The structure of the layers of the first capacitor electrode layer 110a, the dielectric layer 112 and the second capacitor electrode layer 110b as illustrated in FIG. 1(d)-(f) may be repeated one or more timesdepending on specific application requirements.

As illustrated in FIG. 1(g), a second insulation layer 108 b is formedin the trench 106. In this example, second insulation layer 108 b isformed on top of at least part of second conductive layer 110 b. In atleast one implementation, the second insulation layer 108 b is formedconformally on top of second conductive layer 110 b. In this example,second insulation layer 108 b is formed as a thin layer, not filling thetrench 106 completely. Optionally, and as illustrated in this example,second insulation layer 108 b material is also formed on top of thesecond conductive layer 110 b formed on the upper surface 106 b of thefirst side 102 a of substrate 102. A number of different techniques mayalso be used for the forming of the second insulation layer 108 b but itmay be expedient to use the techniques described above in respect of thefirst insulation layer 108 a.

Thus it will be appreciated that FIG. 1(g) illustrates semiconductordevice 100 comprising a second insulation layer 108 b disposed on thesecond capacitor electrode layer 110 b.

As illustrated in FIG. 1(h), a barrier layer 114, such as a diffusionbarrier layer, is formed in the trench 106. In this example, barrierlayer 114 is formed on top of at least part of second insulation layer108 b. In at least one implementation, the barrier layer 114 is formedconformally on top of second insulation layer 108 b. In this example,barrier layer 114 is formed as a thin layer, not filling the trench 106completely. Optionally, and as illustrated in this example, barrierlayer 114 material is also formed on top of the second insulation layer108 b formed on the upper surface 106 b of the first side 102 a ofsubstrate 102. A number of different techniques may also be used for theforming of the barrier layer 114, but one particularly suitabletechnique is ALD. Additionally or alternatively, barrier layer 114 maybe formed by sputtering on the structure shown in FIG. 1(g). A number ofmaterials may be used to form a barrier layer 114, such as TantalumNitride (TaN), Titanium (Ti) or Tantalum (Ta). In one exemplaryarrangement, TiN is used as the barrier layer material. The thickness ofthe layer may be between, for example, 10 nm and 200 nm, 20 nm and 150nm, 30 nm and 100 nm or 40 nm and 75 nm. In one exemplary arrangement,the thickness of the layer is 50 nm.

As illustrated in FIG. 1(i), the trench 106 is filled with conductivematerial 116 a. A number of techniques may be used for the filling ofthe trench 106, and a number of materials, but the inventors have foundthat it is particularly useful to use copper as the conductor, and thatit may be formed by electroplating. As will become apparent, conductivematerial 116 a will function as a through-substrate via conductor 116.In a preferred implementation, conductive material 116 a is arranged asa conductive core 116 b, arranged in the centre axis (not marked in thefigures) of the trench 106. Preferably, conductive material 116 a isarranged concentrically with respect to the centre axis of the trench106.

In FIG. 1(j), a technique, for example, chemical mechanical polishing(CMP) may be used to planarize at least second side 102 b of substrate102 to expose the conductive material 116 a of the via conductive core116 b on the second side 102 b. Once the second side 102 b is thusplanarized, the trench 106 can be considered to have been converted intoa through-substrate via hole 106, given the fact the conductive material116 a is now exposed on both first and second side 102 a, 102 b ofsubstrate 102 for electrical connection thereat. Additionally oralternatively, first side 102 a of substrate 102 is planarized to removethe excess conductive material 116 a projecting above the upper inneredge 106 b of the trench 106. The exemplary TSV with embedded capacitor100 is formed in FIG. 1(j).

Thus it will be appreciated that FIG. 1 illustrates a semiconductordevice 100 comprising a substrate 102 having a through-substrate viahole 106, the through-substrate via hole 106 having formed therein: afirst capacitor electrode layer 110 a and a second capacitor electrodelayer 110 b, and a dielectric material layer 112 disposed between thefirst capacitor electrode layer 110 a and the second capacitor electrodelayer 110 b; and a through-substrate via conductor 116.

It will also be appreciated that FIG. 1 illustrates a method of forminga semiconductor device 100, the semiconductor device 100 comprising athrough-substrate via hole 106, the method comprising forming, in thethrough-substrate via hole 106: a first capacitor electrode layer 110 aand a second capacitor electrode layer 110 b, and a dielectric materiallayer 112 disposed between the first capacitor electrode layer 110 a andthe second capacitor electrode layer 110 b; and a through-substrate viaconductor 116.

Thus, it will be appreciated that FIG. 1(j) illustrates a semiconductordevice 100 comprising the through-substrate via hole 106 having beenformed from a trench 106 formed in a first side 102 a of thesemiconductor substrate 102, the through-substrate via conductor 116comprising a via conductive core 116 b; the first capacitor electrodelayer 110 a, the dielectric material layer 112 and the second capacitorelectrode layer 110 b having been formed in the trench 106, and whereinthe second capacitor electrode layer 110 b surrounds the via conductivecore 116 b.

It will also be appreciated that FIG. 1(j) illustrates the firstcapacitor electrode layer 110 a, the dielectric material layer 112 andthe second capacitor electrode layer 110 b being disposed generally asconcentric layers surrounding the via conductive core.

Thus it will be appreciated that FIG. 1(j) illustrates semiconductordevice 100 comprising a barrier layer 114 disposed on the secondinsulation layer 108 b. It will also be appreciated that barrier layer114 is formed for the trench 106 to be in an unfilled state, the viaconductive core 116 b is formed by filling the trench 106 with aconductive material 116 a and the through-substrate via hole 106 isformed by planarising a second side 102 b of the substrate 102 to exposethe conductive material 116 a of the via conductive core 116 b thereat.

Such techniques offer significant technical advantages, as mentionedabove. In particular, by forming the through-substrate via conductor andthe capacitor electrode layers 110 a, 110 b in the same trench 106,significant savings in respect of the footprint of these components maybe realised. The capacitor thus formed may be considered a trenchcapacitor, e.g. a deep trench capacitor. By combining the deep trenchcapacitor and the through-substrate via conductor together in the sametrench/via hole 106, but by keeping their terminal electrodes separate,both the deep trench capacitor and the through-substrate via conductorcan function independently as if they were built, conventionally,occupying two separate trenches.

Naturally, such advantages may lead to significant cost reductions, inaddition to the space reductions. Further, by simplification of theprocess flows for the formation of a deep trench capacitor and thethrough-substrate via conductor, implementation of the techniquesdisclosed herein may result in fewer processing steps being required.

In the above exemplary techniques, it will be appreciated that severalbuffering layers—including the capacitor electrode and dielectriclayers—are disposed between the substrate 102 itself and thethrough-substrate via conductor 116. With such an arrangement, anyproblems which might be caused by thermal-mechanical stresses may bemitigated.

In addition, a higher capacitance density may be realised. FIG. 2(a)shows a conventional TSV when compared with a TSV with embeddedcapacitor formed in accordance with the techniques described herein. Theformation of the through-substrate via conductor 116 and the capacitorelectrode layers in the same trench 106 may result in a semiconductordevice 100 with a higher capacitance density than a conventional TSV.For instance, it will be seen that the pitch P1 of the conventional TSVis not much greater than the pitch P2 of the TSV with embedded capacitorformed according to the techniques described herein.

FIG. 2(b) illustrates a construction architecture of a simplifiedversion of the TSV with embedded capacitor. In this arrangement, oneinsulation layer and one electrode layer may be removed, and theconductive core may serve as the second electrode layer. Alsoillustrated is the dielectric (in this example, a high-k dielectric) asformed with the other layers on the substrate. R_core denotes the radiusof the through-substrate via core and R_total denotes the total radiusof the trench.

FIG. 2(c) illustrates respective construction architectures of theconventional TSV and the TSV with the embedded capacitor as describedherein provided with two electrode layers and two insulation layers. Thearchitecture of the conventional TSV is simply made up from theconductor core and the insulation layer formed on the substrate.

In contrast, the architecture of the TSV with the embedded capacitorformed according to the techniques described herein comprises the layersof (in the direction moving out from the centre): core, secondinsulation layer, second electrode layer, dielectric layer, firstelectrode layer, first insulation layer, formed on the substrate.

As also illustrated in FIG. 2(c) the footprint area for forming separateconventional TSVs and separate trench capacitors is greater than thefootprint area required for forming a corresponding number of TSVs withembedded capacitors according to the techniques disclosed herein.

Analytical equations have been derived for estimation of capacitancedensity when different geometries and materials are applied.

${{Effective}\mspace{14mu}{Capacitance}\mspace{14mu}{Density}} = \frac{C_{MIM}}{P_{2}^{2} - P_{1}^{2}}$$C_{MIM} = \frac{2{\pi ɛ}_{highk}ɛ_{0} \times H}{\ln\left( \frac{{\frac{1}{2}D_{core}} + T_{highk}}{\frac{1}{2}D_{core}} \right)}$$P_{1} = {4 \times \left( {{\frac{1}{2}D_{core}} + T_{oxide}} \right)}$$P_{2} = {4 \times \left( {{\frac{1}{2}D_{core}} + T_{highk} + T_{electrode} + T_{oxide}} \right)}$

-   -   where:    -   H: Height/depth of trench    -   D_core: Diameter of TSV core=2*R_core    -   T_highk: thickness of high k dielectric layer (which may be, as        mentioned above, Al₂O₃)    -   T_oxide: thickness of oxide layer (which may be, as mentioned        above, SiO₂)    -   T_electrode: thickness of electrode (which may be, as mentioned        above, TiN)

It may be preferable that the core area of the conventional TSV isapproximately equal to the core area of the novel TSV/trench capacitoras herein described.

It may be preferable that the pitch of the novel TSV/trench capacitor asherein described is approximately equal to twice the diameter of theTSV/trench capacitor. It is preferable that the coefficient is greaterthan one, so that neighbouring patterns do not overlap.

Table 1 illustrates some exemplary values for the parameters definedabove.

TABLE 1 ε_(highk) 9 (Al₂O₃) R_(core) 5, 10, 15, 20, 25 μm T_(highk) 30nm T_(electrode) 50 nm T_(oxide) 500 nm H 50 μm

FIG. 3 illustrates an exemplary semiconductor substrate (“chip”) stack300 with one or more of the substrates having been formed in accordancewith the techniques described with respect to FIG. 1. In the example ofFIG. 3, the chip stack 300 comprises a decoupling capacitor module 302for a power distribution network (PDN) as a large amount of capacitanceis required for a low impedance PDN. Chip stack 300 also comprises anintegrated voltage regulator module 304. Stable, large value capacitorsare required for integration of the power system. Chip stack 300 furthercomprises a radio frequency circuit module 306, and capacitors withvertical electrical interconnects enable the 3D integration of CMOS-RFchips. Chip stack 300 comprises on-chip energy storage element modules308. Arrays of on-chip energy storage element modules 308 may provideultra-high capacitance to store energy.

It can be derived from the simulation and measurement results shown inFIG. 4(a), that if the above exemplary techniques are applied as that ofdeep trench capacitor, the capacitance density can be further boosted bymore than 2 times [1]. It is to be noted that there is a discrepancybetween the simulation and measurement values for trench diameters below30 μm. This may be attributed to reactive ion etching loading effectand/or experiments of trenches with different diameters being conductedon the same wafer. It is preferred for the trenches to have the samedepth. Although they may be processed together, the etching chemicalsmay enter more easily into trenches with larger diameters, so trencheswith those larger diameters are etched more quickly than those withsmaller diameters. However, in real-life manufacturing situations, thedispersion between modelling and experiments can be eliminated, thusmeaning the model remains valid.

FIG. 4(b) illustrates a superposition of the two pitch sizes P1 and P2from FIG. 2(a) above. The effective capacitance density of the TSV withembedded capacitor shown in FIG. 4(b) is around 320 nF/mm². A deeptrench capacitor [1] has an effective capacitance density of 440 nF/mm².Following the results derived in FIG. 4(a), the effective capacitancedensity of a TSV with embedded deep trench capacitor may be around 1200nF/mm². The values from [1] for the specifications for the trenchparameters may be compared with the values from Table 1 above for thenew TSV/embedded capacitor.

TABLE 2 ε_(highk) 9 (Al₂O₃) R_(core) 0.75 μm T_(highk) 10 nmT_(electrode) 20 nm T_(oxide) 0 H 30 μm N 2

Turning now to FIG. 5, this provides a series of diagrams illustratingthe forming of another exemplary semiconductor device 100.

Other techniques are contemplated, where one or more steps listed beloware omitted, and/or one or more other process steps are added.

A trench is firstly formed in a silicon substrate, through, for example,lithography and/or etching. It can be 3 μm wide and 30 μm deep.

A low-K dielectric layer can be deposited conformally on sidewalls andbottom of trench by, for example, atomic layer deposition (ALD). SiO₂can be chosen as low-K material and thickness can be 0.1 μm. (FIG. 5a )

A conductive layer can be formed by, for example, ALD on the existingstructure. And it may be assigned to be terminal electrode 1. TiN can bechosen as the first conductive layer material and the thickness can be0.5 μm.

Another low-K dielectric layer can be formed as in FIG. 5(a), which canbe 0.1 μm thick SiO₂ (FIG. 5b ).

A different conductive layer can be deposited by, for example, ALD.TaSiN can be chosen as the second conductive layer material andthickness can be 20 nm.

A thin high-K dielectric layer can be deposited over previous layers.Al₂O₃ can be chosen as the high-K material and the thickness can be 10nm.

A structure of “first conductive layer/high-K/second conductive layer”can be repeated one or more times until the trench is wholly orpartially filled.

Chemical mechanical polishing (CMP) can be used to planarize the surfaceand remove the overburden to expose the substrate surface. (FIG. 5c )

A mask is put on the surface where the first conductive layer isselectively etched by, for example, SC₂ and the second conductive layeris selectively etched by, for example, HF.

A SiO₂ layer can be deposited to cover one or more of the smalltrenches. (FIG. 5d ) The substrate surface may be exposed by, forexample, CMP.

Electrode Contacts, Al, are patterned according to the desired function.(FIG. 5e )

Back-grinding of the substrate may be applied. This can be used, forexample, to expose the outer-most conductive layer, perhaps only thatlayer.

Another electrode contact of Al may be patterned on the back side. (FIG.5f )

FIG. 5g illustrates the formed semiconductor device. In thisarrangement, terminal electrode 1 functions as the through-substrate viaconductor, and terminal electrode 2 and the ground electrode togetherfunction as the capacitor electrodes.

With the above techniques, there may be less TSV capacitance variance.Due to the MOS structure of the conventional TSV, its parasiticcapacitance varies under different biasing conditions, which degradesthe circuit signal integrity. With the addition of the inner TSVcapacitor, a more stable TSV capacitance value can be achieved in alloperational regions. As the thickness of copper layer drops from, forexample, 5 μm (fully filled) to, for example, 1 μm, its totalcapacitance increases due to the existence of the inner capacitor, shownin Table 3 and FIG. 6.

TABLE 3 Stabilized total capacitance Enhanced Original Enhanced InnerOriginal Capacitance Total Total Thickness Capacitance CapacitanceVariation (Inner Capacitance Capacitance (μm) (pF) Variation Capacitance× 10) (pF) (pF) 1 0.085 19.35% 3.93% 0.195 0.960 2 0.058 22.46% 5.47%0.168 0.690 3 0.033 26.38% 8.58% 0.143 0.440 4 0.012 30.93% 16.40% 0.1220.230 5 0 34.30% 34.30% 0.110 0.110Total Capacitance=C _(outer) +C _(inner)where C_(outer) refers to a MOS capacitor, and C_(inner) is a MIMcapacitor. Since the MIM capacitor is not sensitive to biasingconditions, the increase in stable C_(inner) could help mitigate thedifference of total capacitance.

Capacitors may be located nearer to the interconnects, thus lessparasitic components are involved. One of the high quality on-chipcapacitor applications is to decouple the noise in the powerdistribution network of integrated circuits. FIG. 7 shows a first curvedemonstrating the variation of the impedance of embedded capacitors inTSV with respect to frequency, which can exhibit capacitive componentbehaviour even beyond 10 GHz. FIG. 7 also shows a second curvedemonstrating the variation of phase with respect to frequency.

Arrays of TSVs may be inserted in the power distribution networks, asshown in FIG. 8. FIG. 9 shows that an 8Ω impedance peak at 3 GHz can besuppressed to achieve a target impedance level as low as 0.01 Ω in SPICEsimulation.

Normal stress components along the X, Y, Z directions are compared inFIG. 10 with decreasing copper layer thickness. In addition, FIG. 11shows that transistors are also less affected by the piezo-resistiveeffect due to stress in Cu TSVs.

It will be appreciated that the invention has been described by way ofexample only and that various modifications may be made to thetechniques described above without departing from the spirit and scopeof the invention.

REFERENCE

-   1. J. Klootwijk, K. Jinesh, W. Dekkers, J. Verhoeven, F. van den    Heuvel, H. Kim, D. Blin, M. Verheijen, R. Weemaes, M. Kaiser, J.    Ruigrok, and F. Roozeboom, “Ultrahigh Capacitance Density for    Multiple ALD-Grown MIM Capacitor Stacks in 3-D Silicon”, IEEE    Electron Device Lett., vol. 29, no. 7, pp. 740-742, 2008.

The invention claimed is:
 1. A semiconductor device comprising asubstrate having a through-substrate via hole, the through-substrate viahole having formed therein: a capacitor comprising: a first capacitorelectrode layer and a second capacitor electrode layer, and a dielectricmaterial layer disposed between the first capacitor electrode layer andthe second capacitor electrode layer; a through-substrate via conductor,wherein the second capacitor electrode layer is disposed between thefirst capacitor electrode layer and the through-substrate via conductor,the through-substrate via hole having been formed from a trench formedin a first side of the substrate, the through-substrate via conductorcomprising a via conductive core; the first capacitor electrode layer,the dielectric material layer and the second capacitor electrode layerhaving been formed in the trench, and wherein the second capacitorelectrode layer surrounds the via conductive core; an insulation layerdisposed on the second capacitor electrode layer and in between thesecond capacitor electrode layer and the through-substrate viaconductor, the insulation layer being the only layer of a dielectricmaterial arranged between the second capacitor electrode layer and thethrough-substrate via conductor; and a further insulation layer disposedon an inside surface of the trench, the first capacitor electrode layerbeing disposed on the further insulation layer, wherein the capacitorand the through-substrate via conductor are electrically isolated fromone another.
 2. The semiconductor device of claim 1, wherein thesemiconductor device comprises a barrier layer disposed on theinsulation layer that is disposed on the second capacitor electrodelayer.
 3. The semiconductor device of claim 2, the barrier layer havingbeen formed for the trench to be in an unfilled state, the viaconductive core having been formed by filling the trench with aconductive material and the through-substrate via hole having beenformed by planarising a second side of the substrate to expose theconductive material of the via conductive core thereat.
 4. A method offorming a semiconductor device, the semiconductor device comprising asubstrate having a through-substrate via hole, the method comprisingforming, in the through-substrate via hole: a capacitor comprising: afirst capacitor electrode layer and a second capacitor electrode layer,and a dielectric material layer disposed between the first capacitorelectrode layer and the second capacitor electrode layer; and athrough-substrate via conductor, wherein the second capacitor electrodelayer is disposed between the first capacitor electrode layer and thethrough-substrate via conductor, the through-substrate via hole havingbeen formed from a trench formed in a first side of the substrate, thethrough-substrate via conductor comprising a via conductive core, thefirst capacitor electrode layer, the dielectric material layer and thesecond capacitor electrode layer having been formed in the trench,wherein the second capacitor electrode layer surrounds the viaconductive core, and wherein the first capacitor electrode layer, thedielectric material layer and the second capacitor electrode layer aredisposed generally as concentric layers surrounding the via conductivecore, wherein the capacitor and the through-substrate via conductor areelectrically isolated from one another, wherein the method furthercomprises: forming an insulation layer disposed on the second capacitorelectrode layer and in between the second capacitor electrode layer andthe through-substrate via conductor, the insulation layer being the onlylayer of a dielectric material arranged between the second capacitorelectrode layer and the through-substrate via conductor; and forming afurther insulation layer disposed on an inside surface of the trench,the first capacitor electrode layer being disposed on the furtherinsulation layer.
 5. A semiconductor device comprising a substratehaving a through-substrate via hole, the through-substrate via holehaving formed therein: a capacitor comprising: a first capacitorelectrode layer and a second capacitor electrode layer, and a dielectricmaterial layer disposed between the first capacitor electrode layer andthe second capacitor electrode layer; a through-substrate via conductor,wherein the second capacitor electrode layer is disposed between thefirst capacitor electrode layer and the through-substrate via conductor,the through-substrate via hole having been formed from a trench formedin a first side of the substrate, the through-substrate via conductorcomprising a via conductive core; the first capacitor electrode layer,the dielectric material layer and the second capacitor electrode layerhaving been formed in the trench, wherein the second capacitor electrodelayer surrounds the via conductive core, and wherein the first capacitorelectrode layer, the dielectric material layer and the second capacitorelectrode layer are disposed generally as concentric layers surroundingthe via conductive core; an insulation layer disposed on the secondcapacitor electrode layer and in between the second capacitor electrodelayer and the through-substrate via conductor, the insulation layerbeing the only layer of a dielectric material arranged between thesecond capacitor electrode layer and the through-substrate viaconductor; and a further insulation layer disposed on an inside surfaceof the trench, the first capacitor electrode layer being disposed on thefurther insulation layer, wherein the capacitor and thethrough-substrate via conductor are electrically isolated from oneanother.
 6. A semiconductor device comprising a substrate having athrough-substrate via hole, the through-substrate via hole having formedtherein: a first capacitor electrode layer and a second capacitorelectrode layer, and a dielectric material layer disposed between thefirst capacitor electrode layer and the second capacitor electrodelayer; and a through-substrate via conductor, the through-substrate viahole having been formed from a trench formed in a first side of thesubstrate, the through-substrate via conductor comprising a viaconductive core, the first capacitor electrode layer, the dielectricmaterial layer and the second capacitor electrode layer having beenformed in the trench, and wherein the second capacitor electrode layersurrounds the via conductive core, and the first capacitor electrodelayer, the dielectric material layer and the second capacitor electrodelayer being disposed generally as concentric layers surrounding the viaconductive core, wherein the semiconductor device further comprises: afirst insulation layer disposed on an inside surface of the trench, thefirst capacitor electrode layer being disposed on the first insulationlayer, a second insulation layer disposed on the second capacitorelectrode layer; and a barrier layer disposed on the second insulationlayer.
 7. A semiconductor device comprising a substrate having athrough-substrate via hole, the through-substrate via hole having formedtherein: a first capacitor electrode layer and a second capacitorelectrode layer, and a dielectric material layer disposed between thefirst capacitor electrode layer and the second capacitor electrodelayer; and a through-substrate via conductor, the through-substrate viahole having been formed from a trench formed in a first side of thesubstrate, the through-substrate via conductor comprising a viaconductive core, the first capacitor electrode layer, the dielectricmaterial layer and the second capacitor electrode layer having beenformed in the trench, and wherein the second capacitor electrode layersurrounds the via conductive core, and wherein the semiconductor devicefurther comprises: a first insulation layer disposed on an insidesurface of the trench, the first capacitor electrode layer beingdisposed on the first insulation layer, a second insulation layerdisposed on the second capacitor electrode layer; and a barrier layerdisposed on the second insulation layer.
 8. A semiconductor devicecomprising a substrate having a through-substrate via hole, thethrough-substrate via hole having formed therein: a capacitorcomprising: a first capacitor electrode layer and a second capacitorelectrode layer, and a dielectric material layer disposed between thefirst capacitor electrode layer and the second capacitor electrodelayer; and a through-substrate via conductor, wherein the capacitor andthe through-substrate via conductor are electrically isolated from oneanother, the through-substrate via hole having been formed from a trenchformed in a first side of the substrate, the through-substrate viaconductor comprising a via conductive core; the first capacitorelectrode layer, the dielectric material layer and the second capacitorelectrode layer having been formed in the trench, and wherein the secondcapacitor electrode layer surrounds the via conductive core, wherein thesemiconductor device further comprises: a first insulation layerdisposed on an inside surface of the trench, the first capacitorelectrode layer being disposed on the first insulation layer, a secondinsulation layer disposed on the second capacitor electrode layer; and abarrier layer disposed on the second insulation layer.
 9. Thesemiconductor device of claim 8, the first capacitor electrode layer,the dielectric material layer and the second capacitor electrode layerbeing disposed generally as concentric layers surrounding the viaconductive core.
 10. The semiconductor device of claim 8, the barrierlayer having been formed for the trench to be in an unfilled state, thevia conductive core having been formed by filling the trench with aconductive material and the through-substrate via hole having beenformed by planarising a second side of the substrate to expose theconductive material of the via conductive core thereat.